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CAT24C128
FEATURES
128-Kb I2C CMOS Serial EEPROM DEVICE DESCRIPTION
The CAT24C128 is a 128-Kb Serial CMOS EEPROM, internally organized as 256 pages of 64 bytes each, for a total of 16,384 bytes of 8 bits each. It features a 64-byte page write buffer and supports both the Standard (100 kHz) as well as Fast (400 kHz) I2C protocol. Write operations can be inhibited by taking the WP pin High (this protects the entire memory).
Supports Standard and Fast I2C Protocol 1.8V to 5.5V Supply Voltage Range 64-Byte Page Write Buffer Hardware Write Protection for entire memory Schmitt Triggers and Noise Suppression Filters
on I2C Bus Inputs (SCL and SDA).
Low power CMOS technology 1,000,000 program/erase cycles 100 year data retention Industrial temperature range RoHS-compliant 8-lead PDIP, SOIC and TSSOP
packages
For Ordering Information details, see page 14.
PIN CONFIGURATION
PDIP (L) SOIC (W) TSSOP (Y)
A0 A1 A2 VSS 1 2 3 4 8 7 6 5 VCC WP SCL SDA
FUNCTIONAL SYMBOL
VCC
SCL
A2, A1, A0 WP
CAT24C128
SDA
For the location of Pin 1, please consult the corresponding package drawing.
PIN FUNCTIONS
VSS
A0, A1, A2 SDA SCL WP VCC VSS
Device Address Inputs Serial Data Input/Output Serial Clock Input Write Protect Input Power Supply Ground
* Catalyst carries the I2C protocol under a license from the Philips Corporation.
(c) 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
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CAT24C128
ABSOLUTE MAXIMUM RATINGS(1) Storage Temperature Voltage on Any Pin with Respect to Ground(2) RELIABILITY CHARACTERISTICS(3) Symbol NEND(4) TDR Parameter Endurance Data Retention Min 1,000,000 100 Units Program/ Erase Cycles Years -65C to +150C -0.5 V to +6.5 V
D.C. OPERATING CHARACTERISTICS VCC = 1.8 V to 5.5 V, TA = -40C to 85C, unless otherwise specified. Symbol ICCR ICCW ISB IL VIL VIH VOL1 VOL2 Parameter Read Current Write Current Standby Current I/O Pin Leakage Input Low Voltage Input High Voltage Output Low Voltage Output Low Voltage VCC 2.5 V, IOL = 3.0 mA VCC < 2.5 V, IOL = 1.0 mA Test Conditions Read at 400 kHz Write All I/O Pins at GND or VCC Pin at GND or VCC -0.5 Min Max 1 3 1 1 VCC x 0.3 Units mA mA A A V V V V
VCC x 0.7 VCC + 0.5 0.4 0.2
PIN IMPEDANCE CHARACTERISTICS VCC = 1.8 V to 5.5 V, TA = -40C to 85C, unless otherwise specified. Symbol CIN(3) CIN(3) IWP(5) Parameter SDA I/O Pin Capacitance Input Capacitance (other pins) WP Input Current Conditions VIN = 0 V VIN = 0 V VIN < VIH VIN > VIH
Note: (1) Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. (2) The DC input voltage on any pin should not be lower than -0.5 V or higher than VCC + 0.5 V. During transitions, the voltage on any pin may undershoot to no less than -1.5 V or overshoot to no more than VCC + 1.5 V, for periods of less than 20 ns. (3) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100 and JEDEC test methods. (4) Page Mode, VCC = 5 V, 25C (5) When not driven, the WP pin is pulled down to GND internally. For improved noise immunity, the internal pull-down is relatively strong; therefore the external driver must be able to supply the pull-down current when attempting to drive the input HIGH. To conserve power, as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x VCC), the strong pull-down reverts to a weak current source.
Max 8 6 200 1
Units pF pF A A
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(c) 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
CAT24C128
A.C. CHARACTERISTICS(1) VCC = 1.8 V to 5.5 V, TA = -40C to 85C. Standard Symbol FSCL tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR tF(2) tSU:STO tBUF tAA tDH Ti(2) tSU:WP tHD:WP tWR tPU(2, 3)
Note: (1) Test conditions according to "A.C. Test Conditions" table. (2) Tested initially and after a design or process change that affects this paramete. (3) tPU is the delay between the time VCC is stable and the device is ready to accept commands.
Fast Min 0.6 1.3 0.6 0.6 0 100 Max 400 Units kHz s s s s s ns 300 300 0.6 1.3 ns ns s s 0.9 100 100 0 2.5 s ns ns s s 5 1 ms ms
Parameter Clock Frequency START Condition Hold Time Low Period of SCL Clock High Period of SCL Clock START Condition Setup Time Data Hold Time Data Setup Time SDA and SCL Rise Time SDA and SCL Fall Time STOP Condition Setup Time Bus Free Time Between STOP and START SCL Low to SDA Data Out Data Out Hold Time Noise Pulse Filtered at SCL and SDA Inputs WP Setup Time WP Hold Time Write Cycle Time Power-up to Ready Mode
Min 4 4.7 4 4.7 0 250
Max 100
1000 300 4 4.7 3.5 100 100 0 2.5 5 1
A.C. TEST CONDITIONS Input Levels Input Rise and Fall Times Input Reference Levels Output Reference Levels Output Load 0.2 x VCC to 0.8 x VCC
50 ns
0.3 x VCC, 0.7 x VCC 0.5 x VCC Current Source: IOL = 3 mA (VCC 2.5 V); IOL = 1 mA (VCC < 2.5 V); CL = 100 pF
(c) 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
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Doc No. 1103, Rev. G
CAT24C128
POWER-ON RESET (POR)
The CAT24C128 incorporates Power-On Reset (POR) circuitry which protects the device against powering up in the wrong state. The CAT24C128 will power up into Standby mode after VCC exceeds the POR trigger level and will power down into Reset mode when VCC drops below the POR trigger level. This bi-directional POR feature protects the device against `brown-out' failure following a temporary loss of power.
I2C BUS PROTOCOL
The I2C bus consists of two `wires', SCL and SDA. The two wires are connected to the VCC supply via pull-up resistors. Master and Slave devices connect to the 2wire bus via their respective SCL and SDA pins. The transmitting device pulls down the SDA line to `transmit' a `0' and releases it to `transmit' a `1'. Data transfer may be initiated only when the bus is not busy (see A.C. Characteristics). During data transfer, the SDA line must remain stable while the SCL line is HIGH. An SDA transition while SCL is HIGH will be interpreted as a START or STOP condition (Figure 1). The START condition precedes all commands. It consists of a HIGH to LOW transition on SDA while SCL is HIGH. The START acts as a `wake-up' call to all receivers. Absent a START, a Slave will not respond to commands. The STOP condition completes all commands. It consists of a LOW to HIGH transition on SDA while SCL is HIGH. Device Addressing The Master initiates data transfer by creating a START condition on the bus. The Master then broadcasts an 8-bit serial Slave address. The first 4 bits of the Slave address are set to 1010, for normal Read/Write operations (Figure 2). The next 3 bits, A2, A1 and A0, select one of 8 possible Slave devices and must match the state of the external address pins. The last bit, R/W, R/ specifies whether a Read (1) or Write (0) operation is to be performed. Acknowledge After processing the Slave address, the Slave responds with an acknowledge (ACK) by pulling down the SDA line during the 9th clock cycle (Figure 3). The Slave will also acknowledge all address bytes and every data byte presented in Write mode. In Read mode the Slave shifts out a data byte, and then releases the SDA line during the 9th clock cycle. As long as the Master acknowledges the data, the Slave will continue transmitting. The Master terminates the session by not acknowledging the last data byte (NoACK) and by issuing a STOP condition. Bus timing is illustrated in Figure 4.
PIN DESCRIPTION
SCL: The Serial Clock input pin accepts the Serial Clock generated by the Master. SDA: The Serial Data I/O pin receives input data and transmits data stored in EEPROM. In transmit mode, this pin is open drain. Data is acquired on the positive edge, and is delivered on the negative edge of SCL. A0, A1 and A2: The Address pins accept the device address. When not driven, these pins are pulled LOW internally. WP: The Write Protect input pin inhibits all write operations, when pulled HIGH. When not driven, this pin is pulled LOW internally.
FUNCTIONAL DESCRIPTION
The CAT24C128 supports the Inter-Integrated Circuit (I2C) Bus data transmission protocol, which defines a device that sends data to the bus as a transmitter and a device receiving data as a receiver. Data flow is controlled by a Master device, which generates the serial clock and all START and STOP conditions. The CAT24C128 acts as a Slave device. Master and Slave alternate as either transmitter or receiver. Up to 8 devices may be connected to the bus as determined by the device address inputs A0, A1, and A2.
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(c) 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
CAT24C128
Figure 1. START/STOP Conditions
SCL
SDA START CONDITION STOP CONDITION
Figure 2. Slave Address Bits
DEVICE ADDRESS 1 0 1 0 A2 A1 A0 R/W
Figure 3. Acknowledge Timing
BUS RELEASE DELAY (TRANSMITTER) SCL FROM MASTER 1 8 9 BUS RELEASE DELAY (RECEIVER)
DATA OUTPUT FROM TRANSMITTER
DATA OUTPUT FROM RECEIVER START ACK DELAY ( tAA) ACK SETUP ( tSU:DAT)
Figure 4. Bus Timing
tF tLOW SCL tSU:STA SDA IN tAA SDA OUT tDH tBUF tHD:STA tHD:DAT tSU:DAT tSU:STO tHIGH tLOW tR
(c) 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
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Doc No. 1103, Rev. G
CAT24C128
WRITE OPERATIONS
Byte Write Upon receiving a Slave address with the R/W bit set R/W to `0', the CAT24C128 will interpret the next two bytes as address bytes These bytes are used to initialize the internal address counter; the 2 most significant bits are `don't care', the next 8 point to one of 256 available pages and the last 6 point to a location within a 64 byte page. A byte following the address bytes will be interpreted as data. The data will be loaded into the Page Write Buffer and will eventually be written to memory at the address specified by the 14 active address bits provided earlier. The CAT24C128 will acknowledge the Slave address, address bytes and data byte. The Master then starts the internal Write cycle by issuing a STOP condition (Figure 5). During the internal Write cycle (tWR), the SDA output will be tri-stated and additional Read or Write requests will be ignored (Figure 6). Page Write By continuing to load data into the Page Write Buffer after the 1st data byte and before issuing the STOP condition, up to 64 bytes can be written simultaneously during one internal Write cycle (Figure 7). If more data bytes are loaded than locations available to the end of page, then loading will continue from the beginning of page, i.e. the page address is latched and the address count automatically increments to and then wrapsaround at the page boundary. Previously loaded data can thus be overwritten by new data. What is eventually written to memory reflects the latest Page Write Buffer contents. Only data loaded within the most recent Page Write sequence will be written to memory. Acknowledge Polling The ready/busy status of the CAT24C128 can be ascertained by sending Read or Write requests immediately following the STOP condition that initiated the internal Write cycle. As long as internal Write is in progress, the CAT24C128 will not acknowledge the Slave address. Hardware Write Protection With the WP pin held HIGH, the entire memory is protected against Write operations. If the WP pin is left floating or is grounded, it has no impact on the operation of the CAT24C128. The state of the WP pin is strobed on the last falling edge of SCL immediately preceding the first data byte (Figure 8). If the WP pin is HIGH during the strobe interval, the CAT24C128 will not acknowledge the data byte and the Write request will be rejected. Delivery State The CAT24C128 is shipped erased, i.e., all bytes are FFh.
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(c) 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
CAT24C128
Figure 5. Byte Write Sequence
BUS ACTIVITY: MASTER S T A R T S SLAVE A C K SLAVE ADDRESS ADDRESS BYTE a13-a8 ADDRESS BYTE a7-a0 DATA BYTE S T O P P A C K A C K A C K
**
* = Don't Care Bit
Figure 6. Write Cycle Timing
SCL
SDA
8th Bit Byte n
ACK tWR STOP CONDITION START CONDITION ADDRESS
Figure 7. Page Write Sequence
BUS ACTIVITY: MASTER S T A R T S SLAVE Don't * = 63 Care Bit P A C K ADDRESS BYTE a13-a8 ADDRESS BYTE a7-a0 DATA BYTE n DATA BYTE n+1 DATA BYTE n+P S T O P P A C K A C K A C K A C K A C K A C K
SLAVE ADDRESS
**
Figure 8. WP Timing
ADDRESS BYTE 1 SCL 8 9 1 DATA BYTE 8
SDA
a7
a0
tSU:WP
d7
d0
WP
tHD:WP
(c) 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
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Doc No. 1103, Rev. G
CAT24C128
READ OPERATIONS
Immediate Read Upon receiving a Slave address with the R/W bit set to R/W `1', the CAT24C128 will interpret this as a request for data residing at the current byte address in memory. The CAT24C128 will acknowledge the Slave address, will immediately shift out the data residing at the current address, and will then wait for the Master to respond. If the Master does not acknowledge the data (NoACK) and then follows up with a STOP condition (Figure 9), the CAT24C128 returns to Standby mode. Selective Read To read data residing at a specific location, the internal address counter must first be initialized as described under Byte Write. If rather than following up the two address bytes with data, the Master instead follows up with an Immediate Read sequence, then the CAT24C128 will use the 14 active addres bits to initialize the internal address counter and will shift out data residing at the corresponding location. If the Master does not acknowledge the data (NoACK) and then follows up with a STOP condition (Figure 10), the CAT24C128 returns to Standby mode. Sequential Read If during a Read session the Master acknowledges the 1st data byte, then the CAT24C128 will continue transmitting data residing at subsequent locations until the Master responds with a NoACK, followed by a STOP (Figure 11). In contrast to Page Write, during Sequential Read the address count will automatically increment to and then wrap-around at end of memory (rather than end of page).
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(c) 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
CAT24C128
Figure 9. Immediate Read Sequence and Timing
N O SLAVE ADDRESS
BUS ACTIVITY: MASTER
S T A R T S
S AT CO KP P
SLAVE
A C K
DATA BYTE
SCL
8
9
SDA
8th Bit DATA OUT NO ACK STOP
Figure 10. Selective Read Sequence
BUS ACTIVITY: MASTER
S T A R T S
SLAVE ADDRESS
ADDRESS BYTE a13-a8
ADDRESS BYTE a7-a0
S T A R T S
SLAVE ADDRESS
N OS AT CO KP P A C K DATA BYTE
SLAVE
* = Don't Care Bit
A C K
**
A C K
A C K
Figure 11. Sequential Read Sequence
BUS ACTIVITY: SLAVE ADDRESS
N O
MASTER
S AT CO KP P
SLAVE
A C K
DATA BYTE n
A C K
DATA BYTE n+1
A C K
DATA BYTE n+2
A C K
DATA BYTE n+x
(c) 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
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Doc No. 1103, Rev. G
CAT24C128
8-LEAD 300 MIL WIDE PLASTIC DIP (L)
E1
D
E
A2
A
A1
L
e b2 b
eB
SYMBOL A A1 A2 b b2 D E E1 e eB L
MIN 0.38 3.05 0.36 1.14 9.02 7.62 6.09 7.87 0.115
NOM
MAX 4.57 3.81 0.56 1.77 10.16 8.25 7.11 9.65 0.150
24C16_8-LEAD_DIP_(300P).eps
0.46
7.87 6.35 2.54 BSC 0.130
For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf.
Notes: 1. All dimensions are in millimeters. 2. Complies with JEDEC Standard MS001. 3. Dimensioning and tolerancing per ANSI Y14.5M-1982
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(c) 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
CAT24C128
8-LEAD 150 MIL WIDE SOIC (W)
E1 E
D A 1 e b A1
h x 45 C
L
SYMBOL A1 A b C D E E1 e h L 1
MIN 0.10 1.35 0.33 0.19 4.80 5.80 3.80
NOM
MAX 0.25 1.75 0.51 0.25 5.00 6.20 4.00
1.27 BSC 0.25 0.40 0 0.50 1.27 8
24C16_8-LEAD_SOIC.eps
For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf.
Notes: 1. All dimensions are in millimeters. 2. Complies with JEDEC specification MS-012.
(c) 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
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Doc No. 1103, Rev. G
CAT24C128
8-LEAD TSSOP (Y)
D
8 5
SEE DETAIL A
c E E1
E/2
1
4
GAGE PLANE
PIN #1 IDENT. 1 A2 L 0.25 SEATING PLANE SEE DETAIL A A
e b
A1
SYMBOL A A1 A2 b c D E E1 e L 1
MIN 0.05 0.80 0.19 0.09 2.90 6.30 4.30 0.50 0.00
NOM
MAX 1.20 0.15 1.05 0.30 0.20 3.10 6.50 4.50 0.75 8.00
0.90
3.00 6.4 4.40 0.65 BSC 0.60
For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf.
Notes: 1. All dimensions are in millimeters. 2. Complies with JEDEC specification MO-153.
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(c) 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
CAT24C128
PACKAGE MARKING
8-Lead PDIP 8-Lead SOIC
24C128LI FYYWWB
24C128WI FYYWWB
CSI 24C128L I YY WW B F
= Catalyst Semiconductor, Inc. = Device Code = Temperature Range = Production Year = Production Week = Product Revision = Lead Finish 4 = NiPdAu
CSI = Catalyst Semiconductor, Inc. 24C128W = Device Code I = Temperature Range YY = Production Year WW = Production Week B = Product Revision F = Lead Finish 4 = NiPdAu
8-Lead TSSOP
YMBF 24128I
Y M B 24128 I F
= Production Year = Production Month = Product Revision = Device Code = Temperature Range = Lead Finish 4 = NiPdAu
(c) 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
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Doc No. 1103, Rev. G
CAT24C128
ORDERING INFORMATION
Prefix CAT Device # 24C128 Suffix Y I -G T3
Company ID
Product Number 24C128
Temperature Range I = Industrial (-40C to +85C)
T: Tape & Reel 3: 3000/Reel
Package L: PDIP W: SOIC, JEDEC Y: TSSOP
Lead Finish G: NiPdAu
Notes: (1) All packages are RoHS-compliant (Lead-free, Halogen-free). (2) The standard lead finish is NiPdAu. (3) The device used in the above example is a CAT24C128YI-GT3 (TSSOP, Industrial Temperature, NiPdAu, Tape & Reel). (4) For additional package and temperature options, please contact your nearest Catalyst Semiconductor Sales office.
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(c) 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
CAT24C128
REVISION HISTORY
Date 10/07/05 11/16/05 02/02/06 03/13/06 04/26/06 Revision Comments A B C D E Initial Issue Update Ordering Information Add Tape and Reel Specifications Update A.C. Characteristics Update Ordering Information Update A.C. Characteristics Update Features Update Device Description Update Pin Configuration Update A.C. Characteristics Update Hardware Write Protecttion Add Figure 6a Add 8-Lead TSSOP Package Drawing Update Ordering Information Add 8-Lead TSSOP Package Marking Update Features Update Device Description Update Pin Configuration Update Ordering Information Update D.C. Operating Characteristics Update Pin Impedance Characteristics Update A.C. Characteristics Add Power-On Reset (POR) Update 8-Lead PDIP Package Drawing Update 8-Lead SOIC Package Drawing Update 8-Lead TSSOP Package Drawing Update Tape and Reel Update Features Update D.C. Operating Characteristics Update Pin Impedance Characteristics Update A.C. Test Conditions Update Power-On Reset (POR) Update Pin Description Update I2C Bus Protocol Update Device Addressing Update Acknowledge Update Write Operations Update Byte Write Update Page Write Update Acknowledge Polling Add Delivery State Update Read Operations Update Selective Read Update Sequential Read Update Figure 1, 2, 3, 5, 6, 6a, 7, 8, 9 and 10 Update Part Marking Update Ordering Information
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05/19/06
F
08/11/06
G
(c) 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
CAT24C128
Copyrights, Trademarks and Patents Trademarks and registered trademarks of Catalyst Semiconductor include each of the following: DPP TM AE2 TM MiniPotTM
Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES. Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a situation where personal injury or death may occur. Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale. Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications and may not be complete.
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(c) 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
Catalyst Semiconductor, Inc. Corporate Headquarters 2975 Stender Way Santa Clara, CA 95054 Phone: 408.542.1000 Fax: 408.542.1200 www.catsemi.com
Publication #: Revison: Issue date:
1103 G 08/11/06

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